A 1-V, 10-bit Rail-to-Rail Successive Approximation Analog-to-Digital Converter in Standard CMOS Technology
نویسندگان
چکیده
Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process are presented. A track-andhold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail trackand-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-rail current-to-voltage converter, performs the DAC function in the second ADC topology whereas a conventional R-2R ladder is used in the first one. Successive approximation and control logic is implemented using of a robust single clock phase D flip flop.
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